Accelerating Garbled Circuits on Network-Attached Cloud FPGAs

July 29, 2026 •

FPGA Security Cloud Computing Garbled Circuits Cryptography

# Accelerating Garbled Circuits on Network-Attached Cloud FPGAs

Secure Multi-Party Computation (SMPC) allows distrusting parties to evaluate a joint function over private inputs without revealing the inputs to one another. **Yao's Garbled Circuits** is one of the fundamental cryptographic protocols enabling SMPC.

However, evaluating large garbled circuits requires millions of symmetric key encryptions (AES operations) and streaming gigabytes of garbled gate tables over network links.

## Leveraging FPGA-Enabled Cloud Testbeds

At **Northeastern University**, in collaboration with the Open Cloud Testbed, we developed custom hardware accelerators deployed on network-attached FPGAs to evaluate garbled circuits at line rate.

### System Architecture

Our setup integrates FPGA nodes equipped with 100Gbps network interfaces (SmartNICs) directly streaming cryptographic circuit gates to hardware pipelines:

1. **Pipeline Execution**: Dedicated AES-NI / AES hardware pipelines on the FPGA process incoming garbled tables in parallel.
2. **Zero-Copy Streaming**: Network packets pass directly from network interface cards into FPGA BRAM queues without CPU host intervention.
3. **Multi-FPGA Scaling**: Workloads are distributed dynamically across multiple network-attached FPGA nodes.

## Highlights & Citations

This research demonstrates that cloud FPGAs can achieve orders of magnitude faster execution compared to CPU-only SMPC implementations, paving the way for scalable privacy-preserving machine learning and confidential computing.

Read more about this project on [Google Scholar](https://scholar.google.com/citations?user=ZD-tEgMAAAAJ&hl=en) and [LinkedIn](https://www.linkedin.com/in/gungormehmet/).

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